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XRD98L23
8-Bit, High-speed Linear CIS/CCD Sensor Signal Processor with Serial Control
November 2002-2
FEATURES
APPLICATIONS
* * * * * * * * * * * * *
8-Bit Resolution, No Missing Codes One-channel 10MSPS Pixel Rate Dual-channel 5MSPS Pixel Rate Three-channel 3 MSPS Pixel Rate 6-bit Programmable Gain Amplifier 8-bit Programmable Offset Adjustment CIS or CCD Compatibility Internal Clamp for CIS or CCD AC Coupled Configurations 3.3V Operation & I/O Compatibility Serial Load Control Registers Low Power CMOS: 75mW-typ Low Cost 20-Lead Packages USB Compliant
* * * *
Check Scanners General Purpose CIS or CCD Imaging Low Cost Data Acquisition Simple and Direct Interface to Canon 600 DPI Sensors
GENERAL DESCRIPTION The XRD98L23 is a complete linear CIS or CCD sensor signal processor on a single monolithic chip. The XRD98L23 includes a high speed 8-bit resolution ADC, a 6-bit Programmable Gain Amplifier with gain adjustment of 1 to 10, and a typical 8-bit programmable input referred offset calibration range of 480mV. In the CCD configuration the input signal is AC coupled with an external capacitor. An internal clamp sets the black level. In the CIS configuration, the clamp switch can be disabled and the CIS output signal is DC coupled from the CIS sensor to the XRD98L23. The CIS signal is level shifted to VRB in order to use the full range of the ADC. In the CIS configuration the input can also be AC coupled similar to the CCD configuration. This enables CIS signals with large black levels to be internally clamped to a DC reference equal to the black level. The DC reference is internally subtracted from the input signal. The CIS configuration can also be used in other applications that do not require CDS function, such as low cost data acquisition.
ORDERING INFORMATION
Package Type 20-Lead SOIC 20-Lead SSOP
Temperature Range 0C to +70C 0C to +70C
Part Number XRD98L23ACD XRD98L23ACU
Rev. 1.00
EXAR Corporation, 48720 Kato Road, Fremont, CA 94538 * (510) 668-7000 * FAX (510) 668-7017 * www.exar.com
XRD98L23
CIS REF Circuit
VBG
AVDD
RED CLAMP
CIS REF Circuit Triple S/H & 3-1 MUX
Power Down DVDD + BUFFER _ PGA VRT RL 8-BIT ADC 8 DATA I/O PORT 8 DB7:0 VREF+
GRN
BLU DC Reference VDCEXT INT/EXT_V DCREF CLP 6-BIT GAIN REGISTERS DC/AC R G B 6 G<5:0> V DCREF VRB
DGND
Power Down
AVDD AGND
8-BIT DAC AGND 8 CIS/CCD 8-BIT OFFSET REGISTERS VRT CIS CCD R G B O<7:0>
AGND SYNCH CLAMP TIMING & CONTROL LOGIC ADCCLK
Figure 1. Functional Block Diagram
Rev. 1.00
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XRD98L23
PIN CONFIGURATION
DVDD DB0 DB1 DB2 DB3 DB4 DB5/SCLK DB6/SDATA DB7/LD
1 2 3 4 5
20 19 18 17 16
AVDD RED GRN BLU VDCEXT VREF+ AGND SYNCH CLAMP ADCCLK
XRD98L23ACD
6 7 8 9 15 14 13 12 11
DGND 10
20-LeadSOIC
PIN DESCRIPTION
Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Symbol DVDD DB0 DB1 DB2 DB3 DB4 DB5/SCLK DB6/SDATA DB7/LD DGND ADCCLK CLAMP SYNCH AGND VREF+ VDCEXT BLU GRN RED AVDD Description Digital VDD (for Output Drivers) Data Output Bit 0 Data Output Bit 1 Data Output Bit 2 Data Output Bit 3 Data Output Bit 4 Data Output Bit 5 & Data Input SCLK Data Output Bit 6 & Data Input SDATA Data Output Bit 7 & LD Digital Ground (for Output Drivers) A/D Converter Clock Clamp and Video Sample Clock Start of New Line and Serial Data Input Control Analog Ground A/D Positive Reference for Decoupling Cap External DC Reference Blue Input Green Input Red Input Analog Power Supply
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3
XRD98L23
ELECTRICAL CHARACTERISTICS Test Conditions: AVDD=DVDD=3.3V, ADCCLK=10MHz, 50% Duty Cycle, TA=25C unless otherwise specified.
Symbol Parameter Min. Typ. Max. Unit Conditions
Power Supplies AVDD DVDD IDD IDDPD RES Fs DNL INL MON VRT VRB DVREF RL PGARES PGAGMIN PGAGMAX PGAGD VBLACK DACRES OFFMIN OFFMAX OFFMIN OFFMAX OFF Analog Power Supply Digital I/O Power Supply Supply Current (total) Power Down Power Supply Current Resolution Maximum Sampling Rate Differential Non-Linearity Integral Non-Linearity Monotonicity Top Reference Voltage Bottom Reference Voltage Differential Reference Voltage (VRT - VRB) Ladder Resistance 300 600 780 PGA & Offset DAC Specifications PGA Resolution Minimum Gain Maximum Gain Gain Adjustment Step Size Black Level Input Adjust Range Offset DAC Resolution Minimum Offset Adjustment Maximum Offset Adjustment Minimum Offset Adjustment Maximum Offset Adjustment Offset Adjustment Step Size -60 8 -180 +200 -350 +100 -120 +360 -240 +240 1.88 -80 +400 -100 +350 6 0.950 9.5 1.0 10.0 0.14 +300 1.35 10.50 Bits V/V V/V V/V mV Bits mV mV mV mV mV Mode 111, D5=0 (Note 1) Mode 111, D5=0 Mode 111, D5=1 (Note 1) Mode 111, D5=1 DC Configuration 0.18 2.1 8 12 0.5 1.0 Yes 2.2 AVDD/10 0.67AVDD 2.6 V V V 3.0 3.0 3.3 3.3 25 3.6 3.6 60 50 V V mA A Bits MSPS LSB LSB DVDD < AVDD VDD=3.0V VDD=3.0V
ADC Specifications
Note 1:
The additional 60 mV of adjustment with respect to the black level input range is needed to compensate for any additional offset introduced by the XRD98L23 Buffer/PGA internally.
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XRD98L23
ELECTRICAL CHARACTERISTICS (CONT'D) Test Conditions: AVDD=DVDD=3.3V, ADCCLK=10MHz, 50% Duty Cycle, TA=25C unless otherwise specified.
Symbol IIL CIN VINPP Parameter Input Leakage Current Input Capacitance AC Input Voltage Range Min. Typ. Max. 100 10 0 AVDD-1.4 Unit nA pF V Conditions
Buffer Specifications
AC Input Voltage Range
0
DVREF
V
VIN
DC Input Voltage Range
-0.1
AVDD-1.4
V
DC Input Voltage Range
VDCEXT-0.1
VDCEXT+ DVREF
V
CIS AC; INT VDCREF Config Reg => XXX010XX Gain=1 (Note 1) CCD AC; INT VDCREF Config Reg => XXX011XX Gain=1 (Note 1) CIS DC; INT VDCREF Config Reg => XXX000XX Gain=1 (Note 2) CIS DC; EXT VDCREF Config Reg => XXX100XX Gain=1 (Note 3) VDCEXT+DVREF < AVDD CIS DC; EXT VDCREF Config Reg => XXX100XX
VDCEXT
External DC Reference
0.3
AVDD/2
V
VINBW VINCT VCLAMP RINT ROFF
Input Bandwidth (Small Signal) Channel to Channel Crosstalk Clamp Voltage 2.1 Clamp Switch On Resistance Clamp Switch Off Resistance 12
10 -60 AGND VRT 180 50 250
MHz dB mV V M CIS (AC) Config CCD (AC) Config
Internal Clamp Specifications
Note 1: VINPP is the signal swing before the external capacitor tied to the MUX inputs. Note 2: The -0.1V minimum is specified in order to accommodate black level signals lower than the external DC reference (clamp) voltage. Note 3: The VDCEXT-0.1V minimum is specified in order to accommodate black level signals lower than the external DC reference voltage.
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XRD98L23
ELECTRICAL CHARACTERISTICS (CONT'D) Test Conditions: AVDD=DVDD=3.3V, ADCCLK=10MHz, 50% Duty Cycle, TA=25C unless otherwise specified.
Symbol SYSDNL SYSLIN SYSGE IRN Parameter System DNL System Linearity System Gain Error Input Referred Noise Input Referred Noise System Timing Specifications tcklw tckhw tckpd tsypw trars tclpw tsclkw tdz tds tdh tdl tap tdv tsa tsa2 tlat tlat VIH VIL IIH IIL CIN Note 1: Note 2: ADCCLK Low Pulse Width ADCCLK High Pulse Width ADCCLK Period SYNCH Pulse Width Rising ADCCLK to rising SYNCH CLAMP Pulse Width SCLK Pulse Width LD Low to SCLK High Input Data Set-up Time Input Data Hold Time SCLK High to LD High Aperture Delay Output Data Valid SYNCH to ADCCLK (3ch) SYNCH to ADCCLK (2ch) Latency Latency Input High Voltage Input Low Voltage High Voltage Input Current Low Voltage Input Current Input Capacitance 5 5 10 AVDD-1.5 0.6 20 20 80 8 6 30 50 100 30 0 30 40 20 20 0 50 ns ns ns ns ns ns ns ns ns ns cycles pixels V V A A pF 3ch Pixel Md 2ch Pixel Md Config 00, 11 Config 01, 10 50 50 ns ns ns ns SYNCH must rise equal to or after ADCCLK, See Figure 18 Note 2 -5.0 1.5 0.5 Min. -1.0 Typ. 0.5 6.0 +5.0 Max. +2.0 Unit LSB LSB % mVrms mVrms Gain=1 Gain=10 Conditions Note 1 No missing codes
System Specifications (MUX + Buffer + PGA + ADC)
Write Timing Specifications
ADC Digital Output Specifications
Digital Input Specifications
System performance is specified for typical digital system timing specifications. The actual minimum `tclpw' is dependent on the external capacitor value, the CIS output impedance. During `clamp' operation, sufficient time needs to be allowed for the external capacitor to charge up to the correct operating level. Refer to the description in Theory of Operation, CIS Config.
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6
XRD98L23
ELECTRICAL CHARACTERISTICS (CONT'D) Test Conditions: AVDD=DVDD=3.3V, ADCCLK=10MHz, 50% Duty Cycle, TA=25C unless otherwise specified.
Symbol
Parameter
Min.
Typ.
Max.
Unit
Conditions
Digital Output Specifications VOH VOL IOz COUT SR Output High Voltage Output Low Voltage Output High-Z Leakage Current Output Capacitance Slew Rate (10% to 90% DVDD) 2 -10 10 15 80 20 10 (%) DVDD (%) DVDD A pF ns CL = 10pF, DVDD = 3.3V IL = 1mA IL = -1mA
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XRD98L23
THEORY OF OPERATION CIS Configuration (Contact Image Sensor) The XRD98L23 has two configurations for CIS applications. Each configuration is set by the control registers accessed through the serial port. Mode 1. DC Coupled If the CIS does not have leading or trailing black pixels as shown in Figure 2, then DC couple the CIS output to the XRD98L23 input.
Optically Shielded Pixels
Valid Pixels
Figure 2. Typical Output CIS Mode Adjust the offset of the CIS (-60 mV to 300 mV) by setting the internal registers of the XRD98L23 to set the black pixel value when the LEDs of the CIS are off. When the LEDs are on, use the XRD98L23 Programmable Gain to maximize the ADCs dynamic range. Figure 3 shows a typical application for a CIS with an offset of -60mV to 300mV.
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XRD98L23
XRD98L23
VDD
VRT C I S RED N/C N/C N/C M U X R L
VRB
Figure 3. Application with Offset in the Range (-60mv to 300mv)
The input is added to VRB before the signal passes through the ADC. If the CIS output is zero, then the output of the ADC will be zero code. This enables the CIS to be referenced to the bottom ladder reference voltage to use the full range of the ADC. Some CIS sensors have an output with an offset voltage of greater than 300mV. If the CIS output is beyond the
offset range of the XRD98L23 (see Offset Control DAC, Pg. 27) set the internal mode registers to external reference. An external reference voltage equal to the value of the CIS offset voltage can be applied to VDCEXT (Figure 4) in order to meet the dynamic range of the XRD98L23. Figure 4 is a diagram of the XRD98L23 in the external reference mode for CIS, DC coupled applications.
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XRD98L23
XRD98L23 VDD
VRT C I S RED N/C N/C VDCEXT DC REFERENCE VRB M U X RL
Figure 4. Application with Offset Greater Than (-60mv to 300mv)
The DC reference voltage applied to VDCEXT does not have to be accurate. The internal offset DAC voltage is still used in this mode for fine adjustment. VDCEXT
cannot be used as an input from the CIS. Any signal applied to VDCEXT will be subtracted from the output signal of the multiplexer.
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10
XRD98L23
VCC (5V - 15V)
19 18 17 16 0.1uF
RED GRN BLU VDCEXT
AVDD C I S
N/C N/C
DB7/LD DB6/SDATA DB5/SCLK DB4 DB3 DB2 DB1 DB0
9 8 7 6 5 4 3 2
4K
ADCCLK CLAMP SYNCH
11 12 13 DVDD (3V)
DIGITAL ASIC
1K
15
VREF+
0.1uF AVDD
0.01uF
20
0.1uF
14
AGND
DGND
10
AGND
XRD98L23
0.01uF
0.1uF
AVDD
DVDD
1
DGND
Figure 5. Typical Application Circuitry CIS DC Coupled Non-Inverted Mode with VDC External Offset Compensation
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XRD98L23
CIS Mode Timing -- DC Coupled (CLAMP disabled)
Pixel N-1 Pixel N Pixel N+1
tap CIS tckpd tckhw tcklw
tap
ADCCLK tdv DB [7:0] tdv N-8 N/A N-7 N/A N-6 N/A N-5 N/A
Figure 6. Timing Diagram for Figure 5
ADCCLK HI LO
Events ADC Sample & PGA Start Tracking next Pixel Data Out Invalid Data Out ADC Track PGA Output ADC Hold/Convert
Table 1.
Mode 2. AC Coupled If the CIS signal has a black reference for the video signal, an external capacitor CEXT is used. When CLAMP (clamp) pin is set high an internal switch allows one side of the external capacitor to be set to ground. It then is level shifted to correspond to the bottom ladder reference voltage of the ADC (Figure 7).
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XRD98L23
XRD98L23
VDD
VRT C I S REXT CEXT RED N/C N/C N/C CLAMP VRB RINT
M U X
R L
Figure 7. CIS AC Coupled Application
This value corresponds to the black reference of the image sensor. When the CLAMP pin is set back to low, the ADC samples the video signal with respect to the black reference. The typical value for the external capacitor is 100pF. This value should be adjusted according to the time constant (Tc) needed in a particular application. The CLAMP pin has an internal 180 ohm (from electrical tabels) impedance (RINT) which is in series with the external capacitor (CEXT).
Therefore, Tc =1/RINTCEXT If the input to the external capacitor has a source impedance (REXT), then: Tc=1/(RINT+REXT)CEXT
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XRD98L23
VCC (5V - 15V)
19 RED 100PF N/C C I S N/C N/C 18 GRN 17 BLU 16 VDCEXT 15 VREF+ AVDD
0.1uF 0.01uF 0.1uF
DB7/LD DB6/SDATA DB5/SCLK DB4 DB3 DB2 DB1 DB0
9 8 7 6 5 4 3 2
ADCCLK CLAMP SYNCH
11 12 13 DVDD (3V)
0.1uF 0.01uF
DIGITAL ASIC
20 AVDD 14 AGND
DVDD DGND
1 10
AGND
XRD98L23
DGND
Figure 8. Typical Application Circuitry CIS AC Coupled Non-Inverted
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XRD98L23
CIS Mode Timing -- AC Coupled (CLAMP enabled)
Pixel N-1 Pixel N Pixel N+1
tap CIS tckpd tckhw tcklw
tap
ADCCLK tdv DB [7.0] tclpw tdv N-8 N/A N-7 N/A N-6 N/A N-5 N/A
CLAMP
Figure 9. Timing Diagram for Figure 8
ADCCLK HI LO
Events ADC Sample & PGA Start Track of next Pixel Data Out Invalid Data Out ADC Track PGA Output ADC Hold/Convert
Table 2.
CLAMP HI LO Events PGA Tracks VCLAMP & CEXT is Charged to VBLACK - VCLAMP, which is equal to VBLACK PGA Tracks VINPP
Table 3.
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15
XRD98L23
Internal CIS Reference Circuit (DB 4 = 1) The XRD98L23 has an internal register reserved for interfacing to the Canon CIS model number CVA60216K. When this register is selected, the VDCEXT (Pin 16) becomes an output voltage of 1.24 volts. This voltage can be directly connected to the VREF (Pin 5) of the Canon sensor. This reduces the amount of components needed for biasing the Canon CIS sensor (the external diodes and resistors typically used in this application have been included inside the XRD98L23 for this mode of operation). Below is a typical application circuit using the XRD98L23 and the Canon CVA60216K CIS sensor.
VCC (5V) DVDD (3V - 5V) 1 2 3 47u F 4 5 19 RED DB7/LD DB6/ SDATA DB5/SCLK DB4 DB3 DB2 DB1 DB0 9 8 7 6 5 4 3 2 6 7 8 10K 9 10 11 ADCCL K CLAM P SYNC H 11 12 13 NPN 10K 16 VDCEX T
CANON CIS SENSOR
VOU T MOD E AGN D VCC VREF SP CLK LED COM LED BLU LED GRN LED RED FGND
N/C N/C
18
GRN
17
BLU
DIGITAL ASIC
12 47u F
15 0.1u F AVD D 20 0.01u F 0.1u F 14
DGND NPN 10K DVDD (3V ) DGND 0.01u F 0.1u F
VREF+
AGN D 0.01u F 100u F
AVD D AGN D
DVDD DGND
1 NPN 10
DGND
AGN D
XRD98L23
DGND DGND
CVA-60216K
Figure 10. Typical Application Circuitry Internal CIS Reference Circuit Mode CANON CIS Sensor, Model #CVA=60216K
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16
XRD98L23
CIS Line-By-Line Rotating Gain and Offset (Configuration DB1 = 1, DB0 = 1) Line-by-line rotating gain and offset minimizes the amount of write cycles per scan. Pre-loaded values of gain and offset can be loaded for each color before the first line is scanned. Each gain and offset is cycled through line-by-line so that the gain and offset do not have to be loaded in between lines. Below is the typical application circuit and timing for this configuration.
VCC (5V - 15V)
19
RED
18
C I S N/C
GRN
17 16
DB7/LD DB6/SDATA DB5/SCLK DB4 DB3 DB2 DB1 DB0
9 8 7 6 5 4 3 2
BLU VDCEXT ADCCLK CLAMP
DIGITAL
11 12 13
ASIC
15 0.1uF AVDD 0.01uF 20 0.1uF 14
VREF+
SYNCH
DVDD (3V) 1 0.1uF 10 0.01uF
AVDD AGND
DVDD DGND
AGND
XRD98L23
DGND
Figure 11. Typical Application Circuitry Internal CIS Rotating Gain and Offset Line-By-Line
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17
XRD98L23
CCD Configuration (Charge Coupled Device) Mode 1. AC Coupled In the CCD configuration of operation, an external capacitor needs to be chosen according to the equations below. The typical value for the external capacitor is 100pF. This value should be adjusted according to the time constant (Tc) needed in a particular application. The CLAMP pin has an internal 180 ohm impedance (RINT) which is in series with the external capacitor (CEXT). Therefore, Tc =1/RINTCEXT If the input to the external capacitor has a load impedance (REXT), then Tc=1/(RINT+REXT)CEXT When CLAMP (clamp) pin is set high an internal switch allows one side of the external capacitor to be set to VRT (Figure 13). This value corresponds to the black reference of the CCD. When the CLAMP pin is set back to low, the ADC samples the video signal with respect to the black reference. The difference between the black reference and the video signal is the actual pixel value of the video content. Since this value is referenced to the top ladder reference voltage of the ADC a zero input signal would yield a full scale output code. Therefore, the output of the conversion is inverted (internally) to correspond to zero scale output code.
CIS Rotating Gain and Offset Line-By-Line (Md 11)
CIS Red Pixel Line Scan Grn Pixel Line Scan Blu Pixel Line Scan
ADCCLK tsypw SYNCH tsa GAIN/ OFFSET Red Gain/Offset Cycle Grn Gain/Offset Cycle Blu Gain/Offset Cycle
Tri-State (SYNCH = LO) LD Reset Internal Mux Color to Red Channel (LD = 110YYYYYY11) Note: Y = Previous State
Figure 12. Timing Diagram for Figure 11
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XRD98L23
XRD98L23
VDD
CLAMP VRT AREA or LINEAR CCD RED N/C N/C N/C M U X RL
VRB
Figure 13. CCD AC Coupled Application
Area or Linear CCD Applications Figure 13, is a block diagram for applications with Area or Linear CCDs (The timing for Area CCDs and B/W CCDs is the same). For Area or Linear CCD applications, a global offset is loaded into the serial port at the beginning of a line. The gain is set to adjust for the highest color intensity of the CCD output. Once the pixel values have been sampled, the gain and offset are adjusted at the beginning of the next line. For example, if there is a line-to-line variation between the black reference pixels, the offset is adjusted. The gain is always adjusted for the highest color intensity.
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19
XRD98L23
VCC (5V - 15V)
19 100PF
RED
C C D
N/C
18
GRN
N/C
17
DB7/LD DB6/SDATA DB5/SCLK DB4 DB3 DB2 DB1 DB0
9 8 7 6 5 4 3 2
BLU
N/C
16
VDCEXT
ADCCLK CLAMP
11 12 13
DIGITAL ASIC
15
VREF+
SYNCH
AVDD 0.01uF 20 0.1uF 14 AVDD AGND DVDD DGND 1 10
DVDD (3V)
AGND
XRD98L23
DGND
Figure 14. Typical Application Circuitry for a Single Channel B/W CCD AC Coupled Inverted Mode
Rev. 1.00
20
0.01uF
0.1uF
0.1uF
XRD98L23
AREA, LINEAR or B/W CCD -- AC Coupled (CLAMP Enabled)
Pixel N-1 CCD Channel N tckpd tckhw ADCCLK tclpw tcklw Pixel N Pixel N+1
tap
tap
CLAMP tdv DB [7:0] N-8 tdv N/A N-7 N/A N-6 N.A
Figure 15. Timing Diagram for Figure 14
Triple Channel CCD Application Figure 16, is a block diagram for pixel-by-pixel applications with triple channel CCDs. During the optically shielded section of a pixel, CLAMP must go high to store the black reference on each capacitor to the input. The gain and offset is automatically rotated to adjust for each channel input. The data is available on the output bus on the falling edge of ADCCLK.
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XRD98L23
XRD98L23
VDD
CLAMP RED/GRN/BLU C C D N/C M U X RL VRT
VRB
Figure 16. CCD AC Coupled Application
Rev. 1.00
22
XRD98L23
VCC (5V - 15V)
19 100PF 18
RED
GRN
C C D
100PF 17 100PF BLU
DB7/LD DB6/SDATA DB5/SCLK DB4 DB3 DB2 DB1 DB0
9 8 7 6 5 4 3 2
N/C
16
VDCEXT
ADCCLK CLAM P
11 12 13
DIGITAL ASIC
15
VREF+
SYNCH
AVDD 20 0.01uF 0.1uF 0.1uF 14 AVDD AGND DVDD DGND 1 10
DVDD (3V) 0.01uF
AGND
XRD98L23
0.1uF
DGND
Figure 17. Typical Application Circuitry Triple Channel CCD AC Coupled Inverted Mode
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XRD98L23
PIXEL-BY-PIXEL 3 CHANNEL CCD -- AC Coupled (CLAMP Enabled)
RED N Pixel N+1 Pixel
GRN N Pixel tclp=10ns BLU N Pixel N+1 Pixel tap ADCCLK TRACK RED (N) trars CLAMP CLAMP CONVERT RED (N) TRACK GRN (N) CONVERT GRN (N) TRACK BLU (N) CONVERT BLU (N) TRACK RED (N+1) Simultaneous Sample CONVERT RED (N+1) N+1 Pixel tclp=10ns
tdv DATA tsa tsypw SYNCH
tdv RED (N-6) N/A
tdv GRN (N-6) N/A
tdv BLU (N-6) N/A
tdv
Figure 18. Timing Diagram for Figure 17
ADCCLK 3rd All HI LO CLAMP HI LO SYNCH HI LO
Events Simultaneous RED/GRN/BLU Sample Every 3rd CLK. Convert RED, S/H GRN, S/H BLU. Data Out Non-valid Data Out ADC Track PGA Output ADC Hold/Convert Events Internal Clamp Enabled Internal RED/GRN/BLU Tracking Enabled Events Reset Internal Mux to Red, Output Bus is Tri-stated Increment Mux Color on Falling Edge of ADCCLK
Table 4.
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XRD98L23
PIXEL-BY-PIXEL 2-CHANNEL CCD
RED N Pixel N+1 Pixel
GRN N Pixel N+1 Pixel
tap ADCCLK TRACK RED (N) trars CLAMP CONVERT RED (N) TRACK GRN (N) CONVERT GRN (N) TRACK RED (NH) CONVERT RED (NH) TRACK GRN (N+1) CONVERT GRN (N+1)
Simultaneous Sample
tdv DATA RED(N_6) tsa2 tsypw SYNCH
tdv N/A
tdv GRN(N-6) N/A
tdv RED(N-5) N/A
tdv
tsypw
Figure 19. Timing Diagram for 2-channel
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XRD98L23
VRT S1, S2 and S3 close when CLAMP is high and open when CLAMP is low
S1 S2 S3 From CCD RED Channel C EXTR
S6
8-Bit ADC S9 closes at rising edge and opens at falling edge of ADCCLK From CCD GRN Channel C EXTG T/H From CCD BLU Channel C EXTB T/H S5 S8 + T/H VRT VCDS = PGAG * [VRT - (VRT - VPIX)] = PGAG * VPIX S4 S7 VRT - VPIX PGA S9
XRD98L23
VBLK CCD Waveform VPIX VBLK - VPIX CLAMP S8 Opens, S4, S5 and S6 close at this rising edge Track BLU Convert BLU Track RED
S8 Opens, S4, S5 and S6 close at this rising edge ADCCLK Track RED
S6 opens, S7 closes at this rising edge Convert RED Track GRN
S7 opens, S8 closes at this rising edge Convert GRN
S4 and S5 open at this falling edge Convert RED
Figure 20. CDS Timing (Triple Channel) Mode: 110 00001110
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XRD98L23
Mode 2. DC Coupled Typical CCDs have outputs with black references. Therefore, DC Coupled is not recommended for CCD applications.
GAIN 10 9 8 7 6 5 4 3 2 1 0 10 20 30 CODE 40 50 60
PGA GAIN TRANSFER CURVE GAIN 1 - 10
Offset Control DAC The offset DAC is controlled by 8-bits. The offset range is 480 mV ranging from -120 mV to +300 mV (when DB5 is set to 0) and -240 mV to +240 mV (when DB5 is set to 1). Therefore, the resolution of the 8-bit offset DAC is 1.88 mV. However, the XRD98L23 has +/- 60 mV reserved for internal offsets. Therefore, the effective range for adjusting for CIS offsets or black reference is 300 mV. The offset adjustment is used primarily to correct for the difference between the black level of the image sensor and the bottom ladder reference voltage (VRB) of the ADC. By adjusting the black level to correspond to VRB, the entire range of the ADC can be used. If the offset of the CIS output is greater than 300 mV an external reference can be applied to VDCEXT. The external reference can be used to adjust for large offsets only when the internal mode is configured through the serial port. Since the offset DAC adjustment is done before the gain stage, it is gain-dependent. For example, if the gain needs to be changed between lines (red to blue, etc.), the offset is calibrated before the signal passes through the PGA. PGA (Programmable Gain Amplifier) DAC The gain of the input waveform is controlled by a 6-Bit PGA. The PGA is used along with the offset DAC for the purpose of using the entire range of the ADC. The PGA has a linear gain from 1 to 10. Figure 20, is a plot of the transfer curve for the PGA gain.
Figure 21. Transfer Curve for the 6-Bit PGA After the signal is level shifted to correspond with the bottom ladder reference voltage, the system can be calibrated such that a white video pixel can represent the top ladder reference voltage to the ADC. This allows for a full scale conversion maximizing the resolution of the ADC. Analog to Digital Converter The ADC is an 8-bit, 10 MSPS analog-to-digital converter for high speed and high accuracy. The ADC uses a subranging architecture to maintain low power consumption at high conversion rates. The output of the ADC is on 8-bit databus. ADCCLK samples the input on its falling edge. After the input is sampled, the data is latched to the output drivers. On the rising edge of the ADCCLK, invalid data is latched to the output drivers. There is an 8 clock cycle latency (Config 00, 11) or 6 pixel count latency (Config 01, 10) for the analog-to-digital converter. The VRT and VRB reference voltages for the ADC are generated internally, unless the external VRT is selected. In the external VRT mode, the VRT voltage is set through the VREF+ pin. This allows the user to select the dynamic range of the ADC.
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XRD98L23
Serial Load Control Registers The serial load registers are controlled by a three wire serial interface through the bi-directional parallel port to reduce the pin count of this device. When SYNCH is set to high, the output bus is tri-stated and the serial interface is activated. DB7/LD, DB5/SCLK and DB6/ SDATA are the three input signals that control this process. The DB7/LD signal is set low to initiate the loading of the internal registers. There are internal registers that are accessed via an 11bit data string. Data is shifted in on the rising edge of SCLK and loaded to the registers on the rising edge of LD. The data on pin DB6/SDATA is latched automatically after eleven DB5/SCLKs have been counted. If eleven clocks are not present on DB5/SCLK before the DB7/LD signal returns high, no data will be loaded into the internal registers. If more than 11 clocks are present on DB5/SCLK, the additional clocks will be ignored. The data corresponding to the first eleven DB5/SCLKs will be loaded only. The first three MSBs choose which internal register will be selected. The remaining 8 LSBs contain the data needed for programming the internal register for a particular configuration. Power-Up State of the Internal Registers The control register settings upon initial power-up are for CIS, DC Coupled configuration (VRT is set to internal, Input DC Reference=AGND and the input to the ADC is selected through the RED channel). Gain is unity and Offset is set to zero. The test modes are disabled in the power-up state.
SYNCH DB7/LD DB5/SCLK DB6/SDATA tdz tds tdh S1 S0 tsclkw tdl
S2
D7
D2
D1
D0
Figure 22. Write Timing
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XRD98L23
Control Registers
Function (Register S2/S1/S0) D7 D6 D5 D4 D3 D2 D1 D0 Power-up State (Note 1) 000000XX
Red Gain (000) Red Offset (001) Grn Gain (010) Grn Offset (011)
G5 (MSB) O7 (MSB) G5 (MSB)
G4
G3
G2
G1
G0 (LSB) O2
X
X
O6
O5
O4
O3
O1
O0 (LSB) X
01000000
G4
G3
G2
G1
G0 (LSB)
X
000000XX
O7 (MSB)
O6
O5
O4
O3
O2
O1
O0 (LSB)
01000000
Blu Gain (100)
G5 (MSB)
G4
G3
G2
G1
G0 (LSB)
X
X
000000XX
Blu Offset (101)
O7 (MSB) POWER DOWN
O6
O5
O4
O3
O2
O1
O0 (LSB)
01000000
Mode (110)
DIGITAL RESET
VRT
INPUT DC REFERENCE (VDCREF) 0: INTERNAL (VDCREF=AGND) 1: EXTERNAL (VDCREF=VDCEXT)
DC/AC
SIGNAL POLARITY
SIGNAL CONFIGURATION
00000000
0: NORMAL 1: POWER DOWN
0: NO RESET 1:RESET (REGISTERS ARE RESET TO POWER-UP STATES)
0: INTERNAL 1: EXTERNAL
0: DC 1: AC
0: NonInverted (CIS) 1: Inverted (CCD/CIS)
00: Single-Channel RED input/gain/offset 01: Single-Channel RED input RED/GRN/BLU gain/offset cycle pixel-by-pixel or dual channel RED/GRN 10: Triple-Channel RED/GRN/BLU input/gain/offset cycle pixel-by-pixel 11: Triple-Channel RED/GRN/BLU input/gain/offset cycle line-by-line
Mode &Test (111)
OUTPUT BUS CONTROL Must be Programmed to 1
OUTPUT DISABLE
OFFSET DAC RANGE 0:-120mV to +360mV 1:-280mV to +240mV
INTERNAL CIS REFERENCE CIRCUIT 0:NORMAL
TEST4
TEST3
TEST2
TEST1
00000000
0:OUTPUTS ENABLED 1:OUTPUTS DISABLED
0: TEST4 DISABLED
0: TEST3 DISABLED
0: TEST2 0:NORMAL DISABLED 1: INPUT OF ADC TIED TO GRN 1: TEST1 ENABLED
1:REFERENCE CIRCUIT ENABLED
1: OUTPUT 1: OUTPUT OF BUFFER OF PGA TIED TO TIED TO BLU VDCEXT
Note :
These are the control register settings upon initial power-up. The previous register settings are retained following a logic power-down initiated by the power down bit except the signal configuration. When de-selecting the power down bit (D7 = 0, Normal), the signal configuration (D5 and D0) has to be reprogrammed.
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XRD98L23
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30
XRD98L23
20 LEAD SHRINK SMALL OUTLINE PACKAGE (5.3 mm SSOP)
Rev. 2.00
D
20
11
E
1 10
H
C A2 Seating Plane e B A1 L A
SYMBOL A A1 A2 B C D E e H L
INCHES MIN MAX 0.067 0.079 0.002 0.006 0.065 0.073 0.009 0.015 0.004 0.010 0.272 0.296 0.197 0.221 0.0256 BSC 0.292 0.323 0.022 0.037 0 8
MILLIMETERS MIN MAX 1.70 2.00 0.05 0.15 1.65 1.85 0.22 0.38 0.09 0.25 6.90 7.50 5.00 5.60 0.65 BSC 7.40 8.20 0.55 0.95 0 8
Note: The control dimension is the inch column
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XRD98L23
NOTICE EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user's specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for in accuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances. Copyright 2000 EXAR Corporation Datasheet November 2002 Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
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